1. Field of the Invention
The present invention relates to a monolithic digital-to-analog converter integrated circuit, and more particularly, to such a digital-to-analog converter circuit utilizing a ladder network for scaling currents contributed to the analog output current by a plurality of bit switches.
2. Description of the Prior Art
Monolithic digital-to-analog converter circuits are well known in the art and typically include a plurality of bit switches each responsive to a particular bit within the input digital word for selectively steering an associated bit switch current to a summing node at which an analog output current is provided. The current contributed to the analog output current by each of the plurality of bit switches is scaled in a binary weighted fashion in accordance with the binary weighting of the particular bit to which each bit switch is responsive.
In order to scale the bit switch currents in a binary weighted fashion, such digital-to-analog converter circuits often utilize a ladder network interconnected with the current source transistors of each of the bit switches. In this manner, the bit switch currents conducted by each of the bit switches is progressively halved starting with the most significant bit switch and moving toward the least significant bit switch. The output node of each of the bit switches is coupled directly to the analog output current terminal.
Several disadvantages result from constructing a monolithic digital-to-analog converter circuit in this manner. First, by directly coupling the output node of each of the plurality of bit switches to the analog output terminal, a significant amount of capacitive loading is coupled thereto, thereby increasing the settling time of the analog output current. Moreover, the ladder network used to scale the bit switch currents is typically formed from a plurality of laser-trimmable resistors; attempts to trim one such resistor in order to adjust the current within one of the bit switches typically results in a variation in the current provided to one or more other bit switches.
Prior art digital-to-analog converter circuits are known wherein a ladder network is coupled to the output nodes of the bit switches rather than to the current source transistors below the bit switches. However, when utilizing such a ladder network within a digital-to-analog converter fabricated as a monolithic integrated circuit, finite resistances within the conductive metal traces etched within the integrated circuit can create undesirable voltage drops which vary in magnitude depending upon the status of the input digital signal. Varying voltage drops can degrade the linearity of the ladder network, i.e., the ability of the ladder network to accurately and consistantly contribute currents of proper binary weighting to the analog output current. Such voltage drops are particularly altered whenever one or more of the more significant bit switches undergoes a transition.
Accordingly, it is an object of the present invention to provide a monolithic digital-to-analog converter integrated circuit having a relatively rapid settling time while maintaining good linearity between the digital input signal and the analog output signal.
It is a further object of the present invention to provide a monolithic digital-to-analog converter integrated circuit wherein a ladder network is utilized to scale current contributions to the analog output current from a plurality of bit switches and is relatively free of linearity errors due to transitions of the bit switches, including transitions of the more significant bit switches.
These and other objects of the present invention will become more apparent to those skilled in the art as the description thereof proceeds.